Computer Architecture
Designing processors and memory systems quantitatively: the iron law, Amdahl's law, benchmarks and power, instruction set design and RISC-V encodings, the five-stage pipeline with forwarding, stalls and precise exceptions, branch prediction from two-bit counters to gshare and tournament predictors, static scheduling, superscalar and VLIW issue, out-of-order execution with renaming, reservation stations and a reorder buffer, cache organization and miss classification, average memory access time and cache optimizations, virtual memory with Sv32 page tables, TLBs and protection, multicore coherence with MESI, false sharing, memory consistency and atomics, data-level parallelism with packed SIMD, RISC-V vectors, GPUs, accelerators and the roofline model, and storage and I/O with flash endurance and DMA, ending in a capstone trade study that chooses the processor for a solar-powered sensor node.
CMP-310 Year 3 3 credits 12 lessons · 4 h 4 min ▶ Video lessons coming soon
Offered by HSM University · Computer Engineering
This is the Canadian version of this course. See the American version.
What you'll learn
- Evaluate processor designs quantitatively with the iron law, CPI decomposition, benchmarks, Amdahl's law and dynamic and static power, and compare candidates on time and energy per task.
- Analyse instruction set design choices, encode and decode RISC-V base and compressed instructions, and explain how ISA features affect code size, implementation and extensibility.
- Trace instructions through a five-stage pipelined datapath, resolve data hazards with forwarding and stalls, compute pipeline CPI, and explain precise exceptions and interrupts.
- Quantify control hazard penalties and compare static, one-bit, two-bit, correlating and tournament branch predictors and branch target buffers by simulation and by added CPI.
- Expose and exploit instruction-level parallelism with loop unrolling, static scheduling, dual-issue superscalar pipelines and VLIW bundles, and estimate their achieved IPC.
- Explain dynamic scheduling with register renaming, reservation stations and a reorder buffer, trace out-of-order issue with in-order commit, and relate speculation to security leaks.
- Design caches by choosing block size, associativity, replacement and write policies, map addresses to tag, index and offset, and classify misses as compulsory, capacity or conflict.
- Compute average memory access time for multilevel hierarchies, and apply compiler and hardware optimizations such as loop interchange, tiling, prefetching and victim caches.
- Translate virtual addresses through multilevel RISC-V page tables, model TLB behaviour, and compare paging, physical memory protection and virtual machines for isolation.
- Explain snooping and directory cache coherence with MESI, diagnose false sharing, reason about memory consistency models and fences, and build atomic synchronization on RISC-V.
- Apply the roofline model to data-parallel kernels, and compare packed SIMD, RISC-V vectors with strip-mining, GPU SIMT execution and domain-specific accelerators.
- Assess storage and I/O choices including flash endurance, polling, interrupts and DMA, and conduct a constrained, weighted and sensitivity-tested trade study for a processor subsystem.
Course content
12 lessons · 4 h 4 min total · final exam
- 1 Quantitative design and computer performance 21 min · quiz
- 2 Instruction set design and RISC-V in depth 20 min · quiz
- 3 The pipelined datapath: forwarding, stalls and exceptions 22 min · quiz
- 4 Control hazards, branch prediction and speculation 20 min · quiz
- 5 Instruction-level parallelism: scheduling, superscalar and VLIW 20 min · quiz
- 6 Out-of-order execution: renaming, reservation stations and the reorder buffer 20 min · quiz
- 7 The memory hierarchy and cache design 19 min · quiz
- 8 Cache performance and optimizations 20 min · quiz
- 9 Virtual memory, TLBs and protection 19 min · quiz
- 10 Multicore processors, cache coherence and memory consistency 21 min · quiz
- 11 Data-level parallelism: SIMD, vectors, GPUs and accelerators 20 min · quiz
- 12 Storage, I/O and a capstone design trade study 22 min · quiz
- E Final exam 20 questions
Requirements
Recommended background. You can start any course at any time.
Description
Designing processors and memory systems quantitatively: the iron law, Amdahl's law, benchmarks and power, instruction set design and RISC-V encodings, the five-stage pipeline with forwarding, stalls and precise exceptions, branch prediction from two-bit counters to gshare and tournament predictors, static scheduling, superscalar and VLIW issue, out-of-order execution with renaming, reservation stations and a reorder buffer, cache organization and miss classification, average memory access time and cache optimizations, virtual memory with Sv32 page tables, TLBs and protection, multicore coherence with MESI, false sharing, memory consistency and atomics, data-level parallelism with packed SIMD, RISC-V vectors, GPUs, accelerators and the roofline model, and storage and I/O with flash endurance and DMA, ending in a capstone trade study that chooses the processor for a solar-powered sensor node.
Part of the Engineering stream, typically taken in year 3.