Electronics for Computer Engineers
The transistor-level electronics behind digital hardware: energy bands, doping, carriers and temperature effects in silicon, diodes for input clamping, ESD and reverse-polarity protection, flyback suppression and LED and optocoupler drive, MOSFET regions with square-law and alpha-power models, on-resistance, subthreshold leakage and short-channel effects, the CMOS inverter transfer curve, switching threshold, noise margins and Schmitt triggers, static CMOS gates, transistor sizing and logical effort, propagation delay with RC and Elmore models, wire delay and repeaters, dynamic power, leakage, DVFS and the end of Dennard scaling, latches, flip-flops, setup and hold constraints, metastability, synchronizer MTBF and clock-domain crossing, SRAM, DRAM and flash cells with endurance-aware storage, logic families, level compatibility and level shifting, MOSFET switches, inductive kickback, soft-start load switches and isolation, and signal and power integrity with reflections, termination, ground bounce and decoupling, with runnable Python calculations throughout and a running case study of a battery-powered sensor node.
CMP-350 Year 3 3 credits 12 lessons · 4 h 31 min ▶ Video lessons coming soon
Offered by HSM University · Computer Engineering
This is the Canadian version of this course. See the American version.
What you'll learn
- Explain energy bands, doping, carrier concentrations and mobility in silicon, and predict how temperature and process variation change the behaviour of digital circuits.
- Apply diodes in digital systems for input clamping, ESD and reverse-polarity protection, flyback suppression and LED and optocoupler drive, and size the associated resistors.
- Describe MOSFET operating regions, calculate drain current and on-resistance with the square-law and alpha-power models, and explain subthreshold conduction and short-channel effects.
- Analyze the CMOS inverter’s transfer curve, calculate its switching threshold and noise margins, size it for a symmetric threshold, and explain regeneration and Schmitt-trigger hysteresis.
- Design static CMOS NAND, NOR and compound gates, size their transistors for equal drive, and use logical effort to size a path and choose its number of stages.
- Estimate propagation delay with RC and Elmore models, explain the quadratic delay of long wires and the benefit of repeaters, and calculate board-level RC timing and clock-period limits.
- Calculate dynamic, short-circuit and leakage power, explain how voltage, frequency and temperature affect each, and evaluate clock gating, power gating, DVFS and regulator choices.
- Explain how latches and flip-flops store data, derive setup and hold constraints, calculate synchronizer MTBF and choose safe clock-domain crossing techniques.
- Describe the operation and trade-offs of SRAM, DRAM and flash cells, calculate SRAM read margins and DRAM sense signals, and design firmware storage strategies for flash endurance.
- Check logic-level compatibility between families, identify back-powering risks, and design level translation with dividers, MOSFET shifters and dual-supply translators, including pull-up sizing.
- Design MOSFET switches, flyback clamps, soft-start load switches and isolated interfaces that let logic control real-world loads safely and efficiently.
- Recognize transmission-line behaviour, calculate reflections and series termination, limit crosstalk and ground bounce, and size a decoupling network against a target impedance.
Course content
12 lessons · 4 h 31 min total · final exam
- 1 Semiconductors for digital designers 22 min · quiz
- 2 Diodes in digital systems: protection, ESD and LEDs 24 min · quiz
- 3 The MOSFET as a switch: operation and models 19 min · quiz
- 4 The CMOS inverter: transfer curve and noise margins 19 min · quiz
- 5 CMOS logic gates and transistor sizing 19 min · quiz
- 6 Propagation delay and RC timing 22 min · quiz
- 7 Power in CMOS: dynamic power, leakage and scaling 22 min · quiz
- 8 Latches, flip-flops and metastability at the circuit level 23 min · quiz
- 9 Memory cells: SRAM, DRAM and flash 26 min · quiz
- 10 Logic families, voltage levels and level shifting 23 min · quiz
- 11 Interfacing to the analog world: drivers, switches and isolation 27 min · quiz
- 12 Signal integrity and power delivery 25 min · quiz
- E Final exam 20 questions
Requirements
Recommended background. You can start any course at any time.
Description
The transistor-level electronics behind digital hardware: energy bands, doping, carriers and temperature effects in silicon, diodes for input clamping, ESD and reverse-polarity protection, flyback suppression and LED and optocoupler drive, MOSFET regions with square-law and alpha-power models, on-resistance, subthreshold leakage and short-channel effects, the CMOS inverter transfer curve, switching threshold, noise margins and Schmitt triggers, static CMOS gates, transistor sizing and logical effort, propagation delay with RC and Elmore models, wire delay and repeaters, dynamic power, leakage, DVFS and the end of Dennard scaling, latches, flip-flops, setup and hold constraints, metastability, synchronizer MTBF and clock-domain crossing, SRAM, DRAM and flash cells with endurance-aware storage, logic families, level compatibility and level shifting, MOSFET switches, inductive kickback, soft-start load switches and isolation, and signal and power integrity with reflections, termination, ground bounce and decoupling, with runnable Python calculations throughout and a running case study of a battery-powered sensor node.
Part of the Engineering stream, typically taken in year 3.