Electronics I

What you'll learn

• Explain conduction in semiconductors with electrons and holes, calculate carrier concentrations in doped silicon, and describe how a pn junction forms its depletion region and built-in voltage.
• Model diodes with the ideal, constant-drop, piecewise-linear and exponential models, solve diode circuits by iteration and load lines, and use the small-signal diode resistance.
• Design half-wave, full-wave and bridge rectifiers with capacitor filters, calculate ripple, diode stresses and inrush, and check supply headroom at low and high line.
• Design Zener shunt regulators by worst-case analysis, select transient voltage suppressors, and analyze clippers, clampers, peak detectors and envelope detectors.
• Design LED drive circuits, use photodiodes with transimpedance amplifiers, find a solar cell's maximum power point, and design optocoupler interfaces using minimum current transfer ratio.
• Explain how a bipolar junction transistor amplifies, identify its operating modes, and use its exponential law, current gain, output characteristics and Early effect.
• Analyze and design stable BJT bias circuits, constant-current sources and saturated transistor switches, including flyback protection for inductive loads.
• Explain MOSFET operation, apply the triode and saturation equations with channel-length modulation, and read power MOSFET datasheet ratings.
• Bias MOSFETs with source degeneration, design low-side and high-side MOSFET switches, and estimate conduction loss, switching time, switching loss and PWM dimming behaviour.
• Derive and apply small-signal models of BJTs and MOSFETs, calculate transconductance, input and output resistances, and state the limits of the small-signal approximation.
• Analyze common-emitter, common-base and common-collector amplifiers and their MOSFET counterparts, including emitter degeneration and the loading of cascaded stages.
• Estimate low- and high-frequency corners with time constants and the Miller effect, draw Bode plots, and carry an amplifier design from specification through worst-case verification and bench testing.