Integrated Circuit Design

What you'll learn

• Describe the integrated circuit design flow from specification to tape-out, explain the roles of process design kits, DRC, LVS and extraction, and estimate die cost, yield and the break-even volume of a custom chip.
• Explain the main steps of a CMOS process, relate design rules, wells and isolation to layout, and design integrated resistors and capacitors while accounting for process spread, matching and latch-up.
• Apply square-law, body-effect and weak-inversion models, and size MOSFETs with the gm/ID method across weak, moderate and strong inversion.
• Derive the voltage transfer characteristic, switching threshold and noise margins of a CMOS inverter, and estimate its delay and its dynamic, short-circuit and leakage power.
• Design static CMOS gates with complementary networks, size them for equal drive, and use logical effort to size and optimize paths of gates.
• Analyse flip-flop setup and hold constraints with clock skew, handle asynchronous inputs with synchronizers, and reduce power with clock gating and leakage-control techniques.
• Plan layouts with stick diagrams and fingering, estimate wire delay with the Elmore model, isolate analog blocks from digital noise, and apply common-centroid layout and Pelgrom's law to matching.
• Design MOS current mirrors, cascode and wide-swing cascode mirrors, constant-gm bias generators and bandgap voltage references, and explain their accuracy limits and the role of trimming.
• Design active-load, follower, cascode and mirror-loaded differential stages, and size an input stage for gain, bandwidth, offset and noise with the gm/ID method.
• Design a two-stage Miller op-amp by hand, place its poles and nulling-resistor zero for a required phase margin, and compare it with a folded-cascode amplifier.
• Design latched comparators and a charge-redistribution SAR converter, and evaluate the effects of capacitor mismatch, kT/C noise and comparator noise on DNL, INL and ENOB.
• Verify a mixed-signal design across corners and with Monte Carlo analysis, plan trim, ESD and latch-up protection and test features, and conduct a tape-out review.