FPGA & Digital System Design
Designing digital systems for FPGAs from architecture to field deployment: the design flow and the FPGA fabric of lookup tables, logic blocks, carry chains, block RAM, DSP slices and routing, with resource estimation; synthesizable Verilog and SystemVerilog for combinational and sequential logic, blocking and non-blocking assignment semantics, latches, resets, state machine coding styles, parameters and generate; self-checking testbenches with bit-accurate reference models, assertions and coverage; datapath and controller design from ASM charts; fixed-point arithmetic, pipelined DSP slices and time-shared decimating FIR filters; memory inference and FIFO design and sizing; clock-domain crossings with synchronizer MTBF, Gray codes and asynchronous FIFOs; static timing analysis, constraints, pipelining and retiming; UART, SPI, valid and ready streaming with skid buffers and video timing; soft processors, SoC FPGAs, DMA and high-level synthesis; and formal verification, on-chip debug and safe field updates, with runnable Python models, Verilog listings and a capstone sensor front-end accelerator.
CMP-450 Year 4 3 credits 12 lessons · 4 h 21 min ▶ Video lessons coming soon
Offered by HSM University · Computer Engineering
This is the Canadian version of this course. See the American version.
What you'll learn
- Describe the FPGA design flow and the architecture of LUTs, logic blocks, carry chains, block RAM, DSP slices, routing and clocking, and estimate a design's resources before coding.
- Write synthesizable combinational SystemVerilog with correct width and sign rules, avoid latches, and apply blocking and non-blocking assignments according to simulation event semantics.
- Code registers, resets, counters, shift registers and finite state machines in standard styles, choose state encodings, and build parameterized hardware with generate constructs.
- Build self-checking testbenches with bit-accurate reference models, constrained random stimulus, concurrent assertions and functional coverage, and avoid testbench races.
- Derive datapaths and controllers from ASM charts, apply register-transfer timing correctly, and choose among iterative, unrolled and pipelined architectures by throughput.
- Design fixed-point arithmetic with correct formats, guard bits, rounding and saturation, map multipliers onto pipelined DSP slices, and implement FIR filters including time-shared and decimating forms.
- Infer block and distributed memories with the intended read behaviour, design synchronous FIFOs, and size FIFOs from worst-case bursts and stalls.
- Analyze clock-domain crossings with the synchronizer MTBF formula and design bit, pulse, handshake, Gray-code and asynchronous FIFO crossings with reset synchronizers.
- Compute setup and hold slack, write clock, input, output and exception constraints, and close timing with pipelining, retiming, fanout control and architectural changes.
- Implement UART, SPI, valid and ready streaming interfaces with skid buffers, and video timing generators, with correct rate and timing calculations.
- Partition functions between hardware and software in soft-processor and SoC FPGA systems, connect them through registers, interrupts and DMA, and evaluate high-level synthesis schedules.
- Verify and debug FPGA designs with formal, lint, CDC, on-chip logic analysis and hardware-in-the-loop methods, and complete, budget and maintain a full sensor front-end accelerator.
Course content
12 lessons · 4 h 21 min total · final exam
- 1 Digital system design flow and FPGA architecture: LUTs, CLBs, BRAM, DSP slices, routing 25 min · quiz
- 2 Verilog/SystemVerilog for synthesis I: combinational logic, always blocks, blocking vs non-blocking 24 min · quiz
- 3 HDL II: sequential logic, FSM coding styles, parameters/generate 21 min · quiz
- 4 Testbenches and simulation: self-checking, assertions 20 min · quiz
- 5 Datapath and controller design: ASM charts 20 min · quiz
- 6 Arithmetic and DSP: fixed-point, pipelined multipliers, FIR 24 min · quiz
- 7 Memories and FIFOs 18 min · quiz
- 8 Clock domains and CDC: synchronizers, async FIFOs, linking to ELE-210 MTBF 24 min · quiz
- 9 Timing closure: STA, constraints, pipelining, retiming 24 min · quiz
- 10 Interfaces: UART, SPI, AXI-style streaming handshakes, video timing 22 min · quiz
- 11 Soft processors, SoC FPGAs and HLS overview 18 min · quiz
- 12 Verification, debug and capstone (NS-5 sensor front-end accelerator) 21 min · quiz
- E Final exam 20 questions
Requirements
Recommended background. You can start any course at any time.
Description
Designing digital systems for FPGAs from architecture to field deployment: the design flow and the FPGA fabric of lookup tables, logic blocks, carry chains, block RAM, DSP slices and routing, with resource estimation; synthesizable Verilog and SystemVerilog for combinational and sequential logic, blocking and non-blocking assignment semantics, latches, resets, state machine coding styles, parameters and generate; self-checking testbenches with bit-accurate reference models, assertions and coverage; datapath and controller design from ASM charts; fixed-point arithmetic, pipelined DSP slices and time-shared decimating FIR filters; memory inference and FIFO design and sizing; clock-domain crossings with synchronizer MTBF, Gray codes and asynchronous FIFOs; static timing analysis, constraints, pipelining and retiming; UART, SPI, valid and ready streaming with skid buffers and video timing; soft processors, SoC FPGAs, DMA and high-level synthesis; and formal verification, on-chip debug and safe field updates, with runnable Python models, Verilog listings and a capstone sensor front-end accelerator.
Part of the Engineering stream, typically taken in year 4.